1. Field of the Invention
The present invention relates to the field of displaying technology, and in particular to an ESL (Etch Stop Layer) TFT (Thin-Film Transistor) substrate structure and a manufacturing method thereof.
2. The Related Arts
In the field of displaying technology, flat panel displays, such as liquid crystal displays (LCDs) and organic light-emitting diode (OLED) displays, are gradually taking the place of cathode ray tube (CRT) displays and are widely used in liquid crystal televisions, mobile phones, personal digital assistants, digital cameras, computer monitors, and notebook computer screens.
A display panel is an important component of LCDs and OLEDs. For display panels of both the LCDs and the OLEDs, they are often composed of a thin-film transistor (TFT) substrate. Taking an LCD display panel as an example, it is generally composed of a TFT substrate, a color filter (CF) substrate, and a liquid crystal layer interposed between the two substrates, of which the principle of operation is that a drive voltage is applied to the TFT substrate and the CF substrate to control molecules of the liquid crystal to rotate in order to refract out light from a backlight module for generating an image.
Currently, the known TFT substrates are generally classified in various types, including coplanar type, etch stop layer (ESL), and back channel etch (BCE).
Referring to FIG. 1, a conventional ESL TFT substrate comprises a base plate 10 and a gate terminal 20, a gate insulation layer 30, an oxide semiconductor layer 40, an etch stop layer 50, a source terminal 60, a drain terminal 62, a passivation protection layer 70, and a pixel electrode 80 that are sequentially formed on the base plate 10.
The ESL TFT substrate shown in FIG. 1 comprises an etch stop layer (ESL) to protect a back channel from being damaged. However, due to errors of accuracy of a manufacturing process (such as alignment error of an exposure operation and line width deviation in an etching operation), the source terminal 61 and the drain terminal 62 must overlap the etch stop layer 50 by predetermined lengths L1, L3, this plus a minimum length L2 of a gap between the source terminal 61 and the drain terminal 62 that is present due to the capability of the state of the art making the actual length of the channel L the sum of L1, L2, and L3, namely L=L1+L2+L3, which is greater than the back channel length of a BCE TFT substrate. The length of the back channel of a BCE TFT is corresponding to the minimum gap length L2 between the source terminal and the drain terminal.
The greater channel length L may deteriorate the electrical conduction performance of the TFT and may also enlarge the overall size of the TFT, leading to reduction of an aperture ratio of pixels and increasing the difficult of pixel design.